MSPI external RAM ECC and SPI CS timing control register
| SPI_SMEM_CS_SETUP | Set this bit to keep SPI_CS low when MSPI is in PREP state. |
| SPI_SMEM_CS_HOLD | Set this bit to keep SPI_CS low when MSPI is in DONE state. |
| SPI_SMEM_CS_SETUP_TIME | (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. |
| SPI_SMEM_CS_HOLD_TIME | SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. |
| SPI_SMEM_ECC_CS_HOLD_TIME | SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM. |
| SPI_SMEM_ECC_SKIP_PAGE_CORNER | 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM. |
| SPI_SMEM_ECC_16TO18_BYTE_EN | Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM. |
| SPI_SMEM_ECC_ERR_INT_EN | Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. |
| SPI_SMEM_CS_HOLD_DELAY | These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. |